24LC01B DATASHEET PDF

The Microchip Technology Inc. The device is organized as one block of x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1. The 24LC01B also has a page write capability for up to 8 bytes of data. Designers of Serial EEPROM applications can enjoy the increased productivity, reduced time to market and rock-solid design that only a well thought out development system can provide.

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Device Selection Table. The Microchip Technology Inc. Low-voltage design. The 24XX01 is available in the standard. Package Types. SCL 1. Block Diagram. HV Generator. Page Latches. Sense Amp. DSJ-page 1. The descriptions of the pins are listed in Table The SDA input is a bidirectional pin used to transfer. For normal data transfer, SDA is allowed to change. Changes during SCL high are. The SCL input is used to synchronize the data transfer.

If tied to V SS , normal memory operation is enabled. If tied to V CC , write operations are inhibited. The entire. Read operations are. DSJ-page 5. Read operations are initiated in the same way as write. There are three basic types. The 24XX01 contains an address counter that. Therefore, if the previous. Upon receipt of. The master will not acknowledge the transfer, but. Random read operations allow the master to access. To perform. This is accomplished by sending the word.

Once the word address is sent, the master generates a. Start condition following the acknowledge. The master then issues the. The master will not acknowledge. Sequential reads are initiated in the same way as a.

To provide sequential reads the 24XX01 contains an. This Address. Pointer allows the entire memory contents to be serially. Bus Activity. Data n. SDA Line. S 1 0 10xxx1. DSJ-page Clock Frequency 24AA01 1. The device is organized as one block of x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1. The 24XX01 also has a page write capability for up to 8 bytes of data. The entire memory will be write-protected. Read operations are not affected. There are three basic types of read operations: current address read, random read and sequential read.

The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX01 discontinues transmission Figure To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX01 as part of a write operation.

Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the inter- nal Address Pointer is set. The 24XX01 will then issue an acknowledge and transmits the 8-bit data word. This directs the 24XX01 to transmit the next sequentially addressed 8-bit word Figure To provide sequential reads the 24XX01 contains an internal Address Pointer which is incremented by one at the completion of each operation.

This Address Pointer allows the entire memory contents to be serially read during one operation. DSJ-page 11 11 Page. Analog Devices.

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